Update 2019 RISC-V talk.

diff --git a/2019-redhat/2019-riscv-talk.txt b/2019-redhat/2019-riscv-talk.txt
index 9bb1824..2bcc16d 100644 (file)
--- a/2019-redhat/2019-riscv-talk.txt
+++ b/2019-redhat/2019-riscv-talk.txt
@@ -118,17 +118,18 @@ Creative Commons license.
 
 [SLIDE: RISC-V OPEN SOURCE IMPLEMENTATIONS]
 
-At least 5 open source implementations:
+At least 7 open source implementations:
 
  * Rocket chip: Simple in-order processor
  * BOOM and BOOMv2: OOO Superscalar processor
  * PicoRV32
+ * Two Western Digital processors
  * Two educational implementations that I won't talk about today
 
 Rocket is the most widely used.  It is written in Chisel which is a
 Scala-based metalanguage that generates Verilog.  PicoRV32 is a lot of
 fun too: It's written in Verilog and can be programmed on to a very
-cheap (under $40) FPGA.
+cheap (under $40) FPGA.  Great for tinkering.
 
 [SLIDE: OTHER PARTS OF THE ECOSYSTEM]
 
@@ -152,10 +153,11 @@ There are still many missing bits:
  * BMC management
  * Standard boot environment (although this is coming together)
 
-There are two emulators:
+There are three emulators:
 
  * QEMU has supported RV64GC since around 2017.
  * Spike is the RISC-V Foundation's cycle-accurate simulator
+ * Fabrice Bellard's emulator
 
 There are ports of the major tools:
 
@@ -208,8 +210,8 @@ current work.
 
 [SLIDE: KOJI]
 
-Nowadays with have a normal Koji builder which shadows Fedora 29, 30
-and Rawhide.
+Nowadays we have a normal Koji builder which shadows Fedora 29, 30 and
+Rawhide.
 
 [SLIDE: FEDORA RISC-V]