Package the RISCV emulator (Spike).

diff --git a/.gitignore b/.gitignore
index cae19c4..aaa7ad0 100644 (file)
--- a/.gitignore
+++ b/.gitignore
@@ -3,6 +3,8 @@
 stamp-*
 
 /stage1-riscv-qemu/riscv-qemu.spec
 stamp-*
 
 /stage1-riscv-qemu/riscv-qemu.spec

+/stage1-riscv-fesvr/riscv-fesvr.spec
+/stage1-riscv-isa-sim/riscv-isa-sim.spec

 /stage2-riscv-gnu-toolchain/riscv-gnu-toolchain.spec
 /stage2-riscv-pk/riscv-pk.spec
 /stage3-kernel/linux-*
 /stage2-riscv-gnu-toolchain/riscv-gnu-toolchain.spec
 /stage2-riscv-pk/riscv-pk.spec
 /stage3-kernel/linux-*

diff --git a/Makefile b/Makefile
index a66af86..edf9786 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -7,6 +7,10 @@
 # https://github.com/riscv/riscv-pk/issues/18#issuecomment-206115996
 RISCV_QEMU_COMMIT               = 94f5eb73091fb4fe272db3e943f173ecc0f78ffd
 RISCV_QEMU_SHORTCOMMIT          = 94f5eb73
 # https://github.com/riscv/riscv-pk/issues/18#issuecomment-206115996
 RISCV_QEMU_COMMIT               = 94f5eb73091fb4fe272db3e943f173ecc0f78ffd
 RISCV_QEMU_SHORTCOMMIT          = 94f5eb73

+RISCV_FESVR_COMMIT              = 0f34d7ad311f78455a674224225f5b3056efba1d
+RISCV_FESVR_SHORTCOMMIT         = 0f34d7ad
+RISCV_ISA_SIM_COMMIT            = 3bfc00ef2a1b1f0b0472a39a866261b00f67027e
+RISCV_ISA_SIM_SHORTCOMMIT       = 3bfc00ef

 RISCV_GNU_TOOLCHAIN_COMMIT      = 728afcddcb0526a0f6560c4032da82805f054d58
 RISCV_GNU_TOOLCHAIN_SHORTCOMMIT = 728afcdd
 RISCV_PK_COMMIT                 = 85ae17aa149b9ea114bdd70cc30ea7e73813fb48
 RISCV_GNU_TOOLCHAIN_COMMIT      = 728afcddcb0526a0f6560c4032da82805f054d58
 RISCV_GNU_TOOLCHAIN_SHORTCOMMIT = 728afcdd
 RISCV_PK_COMMIT                 = 85ae17aa149b9ea114bdd70cc30ea7e73813fb48


@@ -25,7 +29,13 @@ all: stage1 stage2 stage3 stage4
 
 stage1: stage1-riscv-qemu/riscv-qemu-$(RISCV_QEMU_SHORTCOMMIT).tar.gz \
        stage1-riscv-qemu/riscv-qemu.spec \
 
 stage1: stage1-riscv-qemu/riscv-qemu-$(RISCV_QEMU_SHORTCOMMIT).tar.gz \
        stage1-riscv-qemu/riscv-qemu.spec \

-       stamp-riscv-qemu-installed
+       stamp-riscv-qemu-installed \
+       stage1-riscv-fesvr/riscv-fesvr-$(RISCV_FESVR_SHORTCOMMIT).tar.gz \
+       stage1-riscv-fesvr/riscv-fesvr.spec \
+       stamp-riscv-fesvr-installed \
+       stage1-riscv-isa-sim/riscv-isa-sim-$(RISCV_ISA_SIM_SHORTCOMMIT).tar.gz \
+       stage1-riscv-isa-sim/riscv-isa-sim.spec \
+       stamp-riscv-isa-sim-installed

 
 stage1-riscv-qemu/riscv-qemu-$(RISCV_QEMU_SHORTCOMMIT).tar.gz:
        rm -f $@ $@-t
 
 stage1-riscv-qemu/riscv-qemu-$(RISCV_QEMU_SHORTCOMMIT).tar.gz:
        rm -f $@ $@-t


@@ -57,6 +67,56 @@ stamp-riscv-qemu-installed:
        }
        touch $@
 
        }
        touch $@
 

+stage1-riscv-fesvr/riscv-fesvr-$(RISCV_FESVR_SHORTCOMMIT).tar.gz:
+       rm -f $@ $@-t
+       wget -O $@-t 'https://github.com/riscv/riscv-fesvr/archive/$(RISCV_FESVR_COMMIT)/riscv-fesvr-$(RISCV_FESVR_SHORTCOMMIT).tar.gz'
+       mv $@-t $@
+
+stage1-riscv-fesvr/riscv-fesvr.spec: stage1-riscv-fesvr/riscv-fesvr.spec.in
+       sed -e 's/@COMMIT@/$(RISCV_FESVR_COMMIT)/g' \
+           -e 's/@SHORTCOMMIT@/$(RISCV_FESVR_SHORTCOMMIT)/g' \
+           < $^ > $@-t
+       mv $@-t $@
+
+stamp-riscv-fesvr-installed:
+       rm -f $@
+       @rpm -q riscv-fesvr >/dev/null || { \
+         echo "ERROR: You must install riscv-fesvr:"; \
+         echo; \
+         echo "       dnf copr enable rjones/riscv"; \
+         echo "       dnf install riscv-fesvr"; \
+         echo; \
+         echo "OR: you can build it yourself from the stage1-riscv-fesvr directory."; \
+         echo; \
+         exit 1; \
+       }
+       touch $@
+
+stage1-riscv-isa-sim/riscv-isa-sim-$(RISCV_ISA_SIM_SHORTCOMMIT).tar.gz:
+       rm -f $@ $@-t
+       wget -O $@-t 'https://github.com/riscv/riscv-isa-sim/archive/$(RISCV_ISA_SIM_COMMIT)/riscv-isa-sim-$(RISCV_ISA_SIM_SHORTCOMMIT).tar.gz'
+       mv $@-t $@
+
+stage1-riscv-isa-sim/riscv-isa-sim.spec: stage1-riscv-isa-sim/riscv-isa-sim.spec.in
+       sed -e 's/@COMMIT@/$(RISCV_ISA_SIM_COMMIT)/g' \
+           -e 's/@SHORTCOMMIT@/$(RISCV_ISA_SIM_SHORTCOMMIT)/g' \
+           < $^ > $@-t
+       mv $@-t $@
+
+stamp-riscv-isa-sim-installed:
+       rm -f $@
+       @rpm -q riscv-isa-sim >/dev/null || { \
+         echo "ERROR: You must install riscv-isa-sim:"; \
+         echo; \
+         echo "       dnf copr enable rjones/riscv"; \
+         echo "       dnf install riscv-isa-sim"; \
+         echo; \
+         echo "OR: you can build it yourself from the stage1-riscv-isa-sim directory."; \
+         echo; \
+         exit 1; \
+       }
+       touch $@
+

 # Stage 2
 
 stage2: stage2-riscv-gnu-toolchain/riscv-gnu-toolchain-$(RISCV_GNU_TOOLCHAIN_SHORTCOMMIT).tar.gz \
 # Stage 2
 
 stage2: stage2-riscv-gnu-toolchain/riscv-gnu-toolchain-$(RISCV_GNU_TOOLCHAIN_SHORTCOMMIT).tar.gz \

diff --git a/README b/README
index fc00daa..97e5db4 100644 (file)
--- a/README
+++ b/README
@@ -35,7 +35,7 @@ Most users will download binaries.  Of course source will be available
 for [almost*] everything, buildable from source RPMS.
 
 Currently no hardware is available, so you either have to run RISC-V
 for [almost*] everything, buildable from source RPMS.
 
 Currently no hardware is available, so you either have to run RISC-V

-on an FPGA, or use QEMU emulation.
+on an FPGA, or use QEMU/Spike emulation.

 
 For the FPGA option, you will need a Nexys 4 DDR development kit
 costing around US$341, plus an ordinary micro SD card (8+ GB), plus a
 
 For the FPGA option, you will need a Nexys 4 DDR development kit
 costing around US$341, plus an ordinary micro SD card (8+ GB), plus a


@@ -54,6 +54,12 @@ For the QEMU emulation option, see below.
 
   - Network access is available.
 
 
   - Network access is available.
 

+For the Spike emulation option, see below.
+
+  - Spike has unlimited system RAM.
+
+  - No network.
+

 
 [*] Some CPU peripherals use proprietary IP.  The aim is to replace
 these with open equivalents eventually.  Building the FPGA bitstream
 
 [*] Some CPU peripherals use proprietary IP.  The aim is to replace
 these with open equivalents eventually.  Building the FPGA bitstream


@@ -93,8 +99,8 @@ in COPR (https://copr.fedorainfracloud.org/).
 
 However the majority of packages will be built on RISC-V itself.
 Since there are no RISC-V builders, and we cannot really provide them,
 
 However the majority of packages will be built on RISC-V itself.
 Since there are no RISC-V builders, and we cannot really provide them,

-initially developers will be building them on their own FPGAs / QEMUs
-and uploading them.
+initially developers will be building them on their own FPGAs /
+emulators and uploading them.

 
 Getting build infrastructure would be a more long-term aim.
 
 
 Getting build infrastructure would be a more long-term aim.
 


@@ -114,7 +120,12 @@ Status: done http://copr-fe.cloud.fedoraproject.org/coprs/rjones/riscv
 Note this package runs on x86-64 hosts, and is intended for people who
 want to run Fedora/RISC-V but who do not have FPGA/hardware.
 
 Note this package runs on x86-64 hosts, and is intended for people who
 want to run Fedora/RISC-V but who do not have FPGA/hardware.
 

-(1b) Nexys4 DDR FPGA
+(1b) riscv-isa-sim.x86_64: Spike system emulator
+
+Since QEMU is broken at the moment, we must use the slower Spike
+emulator instead.
+
+(1c) Nexys4 DDR FPGA

 
 Various sources, see:
 http://www.lowrisc.org/docs/untether-v0.2/fpga-demo/
 
 Various sources, see:
 http://www.lowrisc.org/docs/untether-v0.2/fpga-demo/

diff --git a/stage1-riscv-fesvr/riscv-fesvr.spec.in b/stage1-riscv-fesvr/riscv-fesvr.spec.in
new file mode 100644 (file)
index 0000000..babac6e
--- /dev/null
+++ b/stage1-riscv-fesvr/riscv-fesvr.spec.in
@@ -0,0 +1,54 @@
+%global debug_package %{nil}
+
+Name:           riscv-fesvr
+Version:        0
+Release:        0.2.git@SHORTCOMMIT@%{?dist}
+Summary:        RISC-V front end server library
+License:        BSD
+
+URL:            https://github.com/riscv/riscv-fesvr
+Source0:        https://github.com/riscv/%{name}/archive/@COMMIT@/%{name}-@SHORTCOMMIT@.tar.gz
+
+BuildRequires:  glibc-devel
+
+# Workaround some problem with RPM dependency generator.
+Provides:       libfesvr.so()(64bit)
+
+
+%description
+This is the RISC-V front end server library.
+
+
+%prep
+%setup -q -n %{name}-@COMMIT@
+
+
+%build
+mkdir build
+pushd build
+../configure --prefix=%{_prefix} --libdir=%{_libdir}
+make
+popd
+
+
+%install
+pushd build
+make install DESTDIR=$RPM_BUILD_ROOT
+popd
+
+# Package ignores libdir, so fix that.
+mv $RPM_BUILD_ROOT%{_prefix}/lib $RPM_BUILD_ROOT%{_libdir}
+
+
+%files
+%doc README.md COPYING LICENSE
+%{_bindir}/elf2hex
+%{_bindir}/fesvr-eth
+%{_bindir}/fesvr-rs232
+%{_bindir}/fesvr-zedboard
+%{_includedir}/fesvr
+%{_libdir}/libfesvr.so
+%{_libdir}/pkgconfig/riscv-fesvr.pc
+
+
+%changelog

diff --git a/stage1-riscv-isa-sim/riscv-isa-sim.spec.in b/stage1-riscv-isa-sim/riscv-isa-sim.spec.in
new file mode 100644 (file)
index 0000000..d72e4d0
--- /dev/null
+++ b/stage1-riscv-isa-sim/riscv-isa-sim.spec.in
@@ -0,0 +1,61 @@
+%global debug_package %{nil}
+
+Name:           riscv-isa-sim
+Version:        0
+Release:        0.1.git@SHORTCOMMIT@%{?dist}
+Summary:        RISC-V emulator (Spike)
+License:        BSD
+
+URL:            https://github.com/riscv/riscv-isa-sim
+Source0:        https://github.com/riscv/%{name}/archive/@COMMIT@/%{name}-@SHORTCOMMIT@.tar.gz
+
+BuildRequires:  glibc-devel
+BuildRequires:  riscv-fesvr
+
+# Workaround for dependency generator.
+Provides:       libriscv.so()(64bit)
+Provides:       libspike_main.so()(64bit)
+Provides:       libdummy_rocc.so()(64bit)
+Provides:       libsoftfloat.so()(64bit)
+
+
+%description
+This is the RISC-V emulator (Spike).
+
+
+%prep
+%setup -q -n %{name}-@COMMIT@
+
+
+%build
+mkdir build
+pushd build
+../configure --prefix=%{_prefix} --libdir=%{_libdir}
+make
+popd
+
+
+%install
+pushd build
+make install DESTDIR=$RPM_BUILD_ROOT
+popd
+
+# Package ignores libdir, so fix that.
+mv $RPM_BUILD_ROOT%{_prefix}/lib $RPM_BUILD_ROOT%{_libdir}
+
+
+%files
+%doc README.md LICENSE
+%{_bindir}/spike
+%{_bindir}/spike-dasm
+%{_bindir}/termios-xspike
+%{_bindir}/xspike
+%{_includedir}/spike
+%{_libdir}/libdummy_rocc.so
+%{_libdir}/libriscv.so
+%{_libdir}/libsoftfloat.so
+%{_libdir}/libspike_main.so
+%{_libdir}/pkgconfig/riscv-*.pc
+
+
+%changelog