--- /dev/null
+*~
+
+/bindings
+/history
--- /dev/null
+<meta http-equiv="Content-Type" content="text/html; charset=utf-8"/>
+<link rel="stylesheet" href="style.css" type="text/css"/>
+<script src="code.js" type="text/javascript"></script>
+
+<div id="titlepage">
+ <p class="title">
+ RISC-V — <br/>
+ <small>free and open Instruction Set Architecture</small>
+ </p>
+ <p>
+ Monday 26th September 2016 <br/>
+ <author>Richard W.M. Jones <br/>
+ <small>< rjones @ redhat.com ></small>
+ </author></p>
+ <p style="text-align: left;">
+ <a href="https://riscv.org/">RISC-V</a> <i>("Risc Five")</i>
+ is <a href="https://en.wikipedia.org/wiki/RISC-V">a new
+ Instruction Set Architecture (ISA) with a BSD license</a> which
+ aims to become the standard open architecture for industry.
+ </p>
+ <p style="text-align: left;">
+ This talk covers: What precisely is offered by RISC-V?
+ <a href="https://fedoraproject.org/wiki/Architectures/RISC-V">Bootstrapping
+ Fedora on RISC-V</a>. The state of RISC-V software development
+ and the community. Are open source ISAs in Red Hat's future?
+ </p>
+</div>
--- /dev/null
+<meta http-equiv="Content-Type" content="text/html; charset=utf-8"/>
+<link rel="stylesheet" href="style.css" type="text/css"/>
+<script src="code.js" type="text/javascript"></script>
+
+<h1>It's real!</h1>
+
+<img src="cores.png"/>
--- /dev/null
+<meta http-equiv="Content-Type" content="text/html; charset=utf-8"/>
+<link rel="stylesheet" href="style.css" type="text/css"/>
+<script src="code.js" type="text/javascript"></script>
+
+<h1>What is RISC-V?</h1>
+
+<ul>
+<li> An open source instruction set
+<li> 32-, 64- and 128-bit versions
+<li> RV64G ≡ RV64IMAFD
+ <ul>
+ <li> <b>I</b>nteger [required]
+ <li> <b>M</b>ultiply/divide
+ <li> <b>A</b>tomics
+ <li> single-precision <b>F</b>loat
+ <li> <b>D</b>ouble-precision float
+ <li> <b>G</b>eneral purpose ≡ IMAFD
+ </ul>
+</ul>
--- /dev/null
+<meta http-equiv="Content-Type" content="text/html; charset=utf-8"/>
+<link rel="stylesheet" href="style.css" type="text/css"/>
+<script src="code.js" type="text/javascript"></script>
+
+<h1>What is RISC-V?</h1>
+
+<pre>
+00370613 addi a2,a4,3
+02c13c23 sd a2,56(sp)
+02d108a3 sb a3,49(sp)
+00274703 lbu a4,2(a4)
+03d00793 li a5,61
+3cf70863 beq a4,a5,1ce28 <main+0x1d68>
+000165b7 lui a1,0x16
+c3058593 addi a1,a1,-976 # 15c30 <__mon_yday+0x24d8>
+00500613 li a2,5
+00000513 li a0,0
+964fe0ef jal 1abd0 <dcgettext@plt>
+00050613 mv a2,a0
+00000593 li a1,0
+00000513 li a0,0
+f75fd0ef jal 1a9f0 <error@plt>
+9901b503 ld a0,-1648(gp) # 16bd8 <color_buf>
+accfe0ef jal 1ad50 <free@plt>
+9981b503 ld a0,-1640(gp) # 16be0 <color_ext_list>
+00050a63 beqz a0,1caa0 <main+0x19e0>
+02053983 ld s3,32(a0)
+abcfe0ef jal 1ad50 <free@plt>
+00098513 mv a0,s3
+ff1ff06f j 1ca8c <main+0x19cc>
+9a0180a3 sb zero,-1631(gp) # 16be9 <print_with_color>
+</pre>
--- /dev/null
+<meta http-equiv="Content-Type" content="text/html; charset=utf-8"/>
+<link rel="stylesheet" href="style.css" type="text/css"/>
+<script src="code.js" type="text/javascript"></script>
+
+<h1>What is RISC-V?</h1>
+
+<blockquote>
+<i>“[RISC-V]'s not supposed to be "different from other architectures".
+It's supposed to be as familiar as possible to compiler writers and
+CPU designers, minimizing novelty and surprises and maximizing
+precedent so that it can become the <b>Standard Boring ISA</b>.”</i> <br/>
+</blockquote>
+<p style="text-align: right; margin-right: 3em;">
+— Stefan O'Rear on <a href="https://groups.google.com/a/groups.riscv.org/forum/#!forum/isa-dev">the isa-dev mailing list</a>
+</p>
--- /dev/null
+<meta http-equiv="Content-Type" content="text/html; charset=utf-8"/>
+<link rel="stylesheet" href="style.css" type="text/css"/>
+<script src="code.js" type="text/javascript"></script>
+
+<h1>What is RISC-V?</h1>
+
+<img src="specs.png"/>
--- /dev/null
+<meta http-equiv="Content-Type" content="text/html; charset=utf-8"/>
+<link rel="stylesheet" href="style.css" type="text/css"/>
+<script src="code.js" type="text/javascript"></script>
+
+<h1>What is RISC-V?</h1>
+
+<ul>
+<li> Rocket (in-order, single-issue)
+<li> BOOM (OOO, up to quad issue)
+<li> Z-scale (similar to ARM Cortex M0-M4)
+<li> Educational
+</ul>
--- /dev/null
+<meta http-equiv="Content-Type" content="text/html; charset=utf-8"/>
+<link rel="stylesheet" href="style.css" type="text/css"/>
+<script src="code.js" type="text/javascript"></script>
+
+<h1>What is RISC-V?</h1>
+
+<pre style="font-size: smaller;">
+val id_illegal_insn = !id_ctrl.legal ||
+ id_ctrl.div && !csr.io.status.isa('m'-'a') ||
+ id_ctrl.amo && !csr.io.status.isa('a'-'a') ||
+ id_ctrl.fp && !(csr.io.status.fs.orR && csr.io.status.isa('f'-'a')) ||
+ id_ctrl.dp && !csr.io.status.isa('d'-'a') ||
+ ibuf.io.inst(0).bits.rvc && !csr.io.status.isa('c'-'a') ||
+ id_ctrl.rocc && !(csr.io.status.xs.orR && csr.io.status.isa('x'-'a'))
+// stall decode for fences (now, for AMO.aq; later, for AMO.rl and FENCE)
+val id_amo_aq = id_inst(0)(26)
+val id_amo_rl = id_inst(0)(25)
+val id_fence_next = id_ctrl.fence || id_ctrl.amo && id_amo_rl
+val id_mem_busy = !io.dmem.ordered || io.dmem.req.valid
+val id_rocc_busy = Bool(usingRoCC) &&
+ (io.rocc.busy || ex_reg_valid && ex_ctrl.rocc ||
+ mem_reg_valid && mem_ctrl.rocc || wb_reg_valid && wb_ctrl.rocc)
+id_reg_fence := id_fence_next || id_reg_fence && id_mem_busy
+val id_do_fence = id_rocc_busy && id_ctrl.fence ||
+ id_mem_busy && (id_ctrl.amo && id_amo_aq || id_ctrl.fence_i || id_reg_fence
+ && (id_ctrl.mem || id_ctrl.rocc) || id_csr_en)
+</pre>
--- /dev/null
+<meta http-equiv="Content-Type" content="text/html; charset=utf-8"/>
+<link rel="stylesheet" href="style.css" type="text/css"/>
+<script src="code.js" type="text/javascript"></script>
+
+<h1>What is RISC-V?</h1>
+
+<ul>
+<li> QEMU (3 forks! none upstream!)
+<li> Spike
+</ul>
--- /dev/null
+<meta http-equiv="Content-Type" content="text/html; charset=utf-8"/>
+<link rel="stylesheet" href="style.css" type="text/css"/>
+<script src="code.js" type="text/javascript"></script>
+
+<h1>What is RISC-V?</h1>
+
+<ul>
+<li> Linux Kernel (forked, 3.14 & 4.1)
+<li> binutils (forked, 2.26, 2.27)
+<li> GCC (forked, 6.1.0, 6.2.0)
+<li> glibc (forked ...)
+</ul>
--- /dev/null
+<meta http-equiv="Content-Type" content="text/html; charset=utf-8"/>
+<link rel="stylesheet" href="style.css" type="text/css"/>
+<script src="code.js" type="text/javascript"></script>
+
+<h1>What is RISC-V?</h1>
+
+<ul>
+<li> LowRISC <i>"Raspberry Pi for grown-ups"</i>
+<li> SiFive
+<li> Numerous FPGA implementations
+<li> Lots of university research groups
+<li> Lots of small commercial development groups
+</ul>
--- /dev/null
+<meta http-equiv="Content-Type" content="text/html; charset=utf-8"/>
+<link rel="stylesheet" href="style.css" type="text/css"/>
+<script src="code.js" type="text/javascript"></script>
+
+<h1>What is RISC-V?</h1>
+
+<ul>
+<li> NVidia
+<li> Google
+<li> AMD
+<li> HPE
+<li> IBM
+<li> Mellanox
+<li> Microsemi
+<li> Microsoft
+<li> Western Digital
+<li> and more
+</ul>
--- /dev/null
+<meta http-equiv="Content-Type" content="text/html; charset=utf-8"/>
+<link rel="stylesheet" href="style.css" type="text/css"/>
+<script src="code.js" type="text/javascript"></script>
+
+<h1>What missing from RISC-V?</h1>
+
+<ul>
+<li> Interrupt controller (but coming soon)
+<li> Serial port
+<li> Ethernet
+<li> Display
+<li> SATA
+<li> DDR4
+<li> PCI (but SiFive have something)
+<li> etc etc etc
+</ul>
+
+<p>
+Not enough to make a real processor or SoC
+</p>
--- /dev/null
+# -*- shell-script -*-
+
+# Colour ls.
+if [ -f /etc/profile.d/colorls.sh ]; then . /etc/profile.d/colorls.sh; fi
+
+# Fancy prompt colours (see
+# https://wiki.archlinux.org/index.php/Color_Bash_Prompt)
+promptcol='\e[0;32m' ;# colour for the prompt
+commandcol='\e[1;31m' ;# colour for the typed command
+outputcol='\e[0m' ;# colour for command output
+
+export PS1="\n\[$promptcol\]\$ \[$commandcol\]"
+
+trap 'echo -ne "$outputcol"' DEBUG
+
+# Load key bindings (if any).
+bind -f $talkdir/bindings
--- /dev/null
+Talk contents:
+
+ - What precisely is offered by RISC-V?
+
+ - Bootstrapping Fedora.
+
+ - The state of RISC-V software development and the community.
+
+ - Are open source ISAs in Red Hat's future?
+
+----------------------------------------------------------------------
+
+Instructions:
+
+fixed size 32 bit instructions
+compressed instructions extension
+32 general purpose registers
+32 floating point registers (extension)
+zero register
+influenced by MIPS
+proven to be patent-free
+
+Boring:
+
+Micro-architecture independent as far as possible
+Micro-op fusion
+No register windows, branch delay slots etc
+Royalty free, no licensing
+
+Specifications:
+
+ User spec 2.0 -> 2.1
+ Priv spec 1.7 -> 1.9/2.0
+
+4 open source core designs, Rocket, BOOM and two others
+ Chisel generates Verilog
+ Includes cache hierarchy
+ Includes coherence between L2 caches
+ Parameterized
+ Targets C++ (simulation), FPGA or ASIC
+ Proprietary tools needed if you go FPGA or ASIC route
+
+Emulators
+
+Toolchain
+
+External projects:
+ LowRISC = "RPi for grown-ups"
+ SiFive
+ Many FPGA implementations
+ Lots of research groups
+ Lots of small dev groups
+
+Some large companies looking: NVidia, Google, AMD, HPE, IBM, Mellanox,
+Microsemi, Microsoft, WD, ...
+
+Missing bits:
+ PLIC (coming)
+ any other sort of hardware, serial, ethernet, display, SATA, DDR, ...
+ PCI (SiFive have done some work)
+ much of this is filled in with proprietary "IP"
+ "Minion cores"
+
+----------------------------------------------------------------------
+
+Fedora
+
+----------------------------------------------------------------------
+
+Software development and the community
+
+----------------------------------------------------------------------
+
+Red Hat
--- /dev/null
+/* Red Hat red is rgb(204,0,0). */
+
+body {
+ background: url(redhat.png) no-repeat;
+ background-position: 98% 0;
+ /* font-size: 28pt; */ /* For max */
+ font-size: 20pt; /* For 1024x768 */
+ /* font-family: liberation, helvetica; */
+ font-family: helvetica;
+}
+
+body td, body th { /* why?? */
+ font-size: 24pt;
+ padding-bottom: 8px;
+}
+
+h1 {
+ color: rgb(204,0,0);
+ /*font-size: 48px;*/
+ font-size: 40px;
+ top: 8;
+ left: 0;
+ border-bottom: 2px solid rgb(204,0,0);
+}
+
+b {
+ color: rgb(204,0,0);
+}
+
+div#titlepage {
+ margin-top: 100px;
+ text-align: center;
+}
+
+div#titlepage p.title {
+ color: rgb(204,0,0);
+ font-weight: bold;
+ font-size: 48px;
+}
+
+div#titlepage author {
+ font-size: 36px;
+}
+
+/* Code */
+pre.code {
+ margin-left: 1em;
+ background: #eee;
+}
+
+code {
+ color: rgb(204,0,0);
+}
+
+/* Bullet points */
+li {
+ padding-bottom: 16px;
+}
+
+/* Logo */
+img#fish {
+ position: absolute;
+ top: 128px;
+ right: 32px;
+ width: 200px;
+ /*height: 256px;*/
+}
\ No newline at end of file
git.annexia.org / riscv-talks.git / commitdiff
