--- /dev/null
+<meta http-equiv="Content-Type" content="text/html; charset=utf-8"/>
+<link rel="stylesheet" href="style.css" type="text/css"/>
+<script src="code.js" type="text/javascript"></script>
+
+<h1>What is RISC-V?</h1>
+
+<pre style="font-size: smaller;">
+val id_illegal_insn = !id_ctrl.legal ||
+ id_ctrl.div && !csr.io.status.isa('m'-'a') ||
+ id_ctrl.amo && !csr.io.status.isa('a'-'a') ||
+ id_ctrl.fp && !(csr.io.status.fs.orR && csr.io.status.isa('f'-'a')) ||
+ id_ctrl.dp && !csr.io.status.isa('d'-'a') ||
+ ibuf.io.inst(0).bits.rvc && !csr.io.status.isa('c'-'a') ||
+ id_ctrl.rocc && !(csr.io.status.xs.orR && csr.io.status.isa('x'-'a'))
+// stall decode for fences (now, for AMO.aq; later, for AMO.rl and FENCE)
+val id_amo_aq = id_inst(0)(26)
+val id_amo_rl = id_inst(0)(25)
+val id_fence_next = id_ctrl.fence || id_ctrl.amo && id_amo_rl
+val id_mem_busy = !io.dmem.ordered || io.dmem.req.valid
+val id_rocc_busy = Bool(usingRoCC) &&
+ (io.rocc.busy || ex_reg_valid && ex_ctrl.rocc ||
+ mem_reg_valid && mem_ctrl.rocc || wb_reg_valid && wb_ctrl.rocc)
+id_reg_fence := id_fence_next || id_reg_fence && id_mem_busy
+val id_do_fence = id_rocc_busy && id_ctrl.fence ||
+ id_mem_busy && (id_ctrl.amo && id_amo_aq || id_ctrl.fence_i || id_reg_fence
+ && (id_ctrl.mem || id_ctrl.rocc) || id_csr_en)
+</pre>