Add short presentation about RISC-V hardware for Koji

[riscv-talks.git] / 2019-redhat / 2019-riscv-talk.txt

diff --git a/2019-redhat/2019-riscv-talk.txt b/2019-redhat/2019-riscv-talk.txt
index 9bb1824..5089f00 100644 (file)
--- a/2019-redhat/2019-riscv-talk.txt
+++ b/2019-redhat/2019-riscv-talk.txt
@@ -118,17 +118,18 @@ Creative Commons license.
 
 [SLIDE: RISC-V OPEN SOURCE IMPLEMENTATIONS]
 
 
 [SLIDE: RISC-V OPEN SOURCE IMPLEMENTATIONS]
 

-At least 5 open source implementations:
+At least 7 open source implementations:

 
  * Rocket chip: Simple in-order processor
  * BOOM and BOOMv2: OOO Superscalar processor
  * PicoRV32
 
  * Rocket chip: Simple in-order processor
  * BOOM and BOOMv2: OOO Superscalar processor
  * PicoRV32

+ * Two Western Digital processors

  * Two educational implementations that I won't talk about today
 
 Rocket is the most widely used.  It is written in Chisel which is a
 Scala-based metalanguage that generates Verilog.  PicoRV32 is a lot of
 fun too: It's written in Verilog and can be programmed on to a very
  * Two educational implementations that I won't talk about today
 
 Rocket is the most widely used.  It is written in Chisel which is a
 Scala-based metalanguage that generates Verilog.  PicoRV32 is a lot of
 fun too: It's written in Verilog and can be programmed on to a very

-cheap (under $40) FPGA.
+cheap (under $40) FPGA.  Great for tinkering.

 
 [SLIDE: OTHER PARTS OF THE ECOSYSTEM]
 
 
 [SLIDE: OTHER PARTS OF THE ECOSYSTEM]
 


@@ -152,10 +153,11 @@ There are still many missing bits:
  * BMC management
  * Standard boot environment (although this is coming together)
 
  * BMC management
  * Standard boot environment (although this is coming together)
 

-There are two emulators:
+There are three emulators:

 
  * QEMU has supported RV64GC since around 2017.
  * Spike is the RISC-V Foundation's cycle-accurate simulator
 
  * QEMU has supported RV64GC since around 2017.
  * Spike is the RISC-V Foundation's cycle-accurate simulator

+ * Fabrice Bellard's emulator

 
 There are ports of the major tools:
 
 
 There are ports of the major tools:
 


@@ -171,6 +173,8 @@ There are ports of the major tools:
 
 I did the first bootstrap of Fedora in September 2016.
 
 
 I did the first bootstrap of Fedora in September 2016.
 

+[SLIDE: BOOTSTRAPPING]
+

 Bootstrapping Fedora is complicated: I started off with an x86-64 disk
 image which could run rpmbuild.  I then removed all of the x86-64
 binaries and libraries.  I replaced them with cross-compiled RISC-V
 Bootstrapping Fedora is complicated: I started off with an x86-64 disk
 image which could run rpmbuild.  I then removed all of the x86-64
 binaries and libraries.  I replaced them with cross-compiled RISC-V


@@ -208,8 +212,8 @@ current work.
 
 [SLIDE: KOJI]
 
 
 [SLIDE: KOJI]
 

-Nowadays with have a normal Koji builder which shadows Fedora 29, 30
-and Rawhide.
+Nowadays we have a normal Koji builder which shadows Fedora 29, 30 and
+Rawhide.

 
 [SLIDE: FEDORA RISC-V]
 
 
 [SLIDE: FEDORA RISC-V]
 


@@ -219,8 +223,6 @@ or under QEMU on your laptop.
 [I will show a demo of Fedora RISC-V, showing that it looks very much
 like Fedora on any other architecture]
 
 [I will show a demo of Fedora RISC-V, showing that it looks very much
 like Fedora on any other architecture]
 

-[SLIDE: DEBIAN]
-

 While we were working on Fedora, we were also working closely with the
 Debian and upstream communities.  Patches and techniques are shared
 with upstream and with Debian.
 While we were working on Fedora, we were also working closely with the
 Debian and upstream communities.  Patches and techniques are shared
 with upstream and with Debian.


@@ -229,6 +231,8 @@ To get involved with Fedora RISC-V please join us on Freenode:
 
  #fedora-riscv
 
 
  #fedora-riscv
 

+[SLIDE: DEBIAN]
+

 
 
 3. Companies making RISC-V hardware
 
 
 3. Companies making RISC-V hardware