1 RISC-V ("Risc Five") is an open source Instruction Set Architecture
2 (ISA). Today I will explain what that means and talk about what we
3 have done to port Fedora and upstream projects to RISC-V.
5 1. Background - What is RISC-V?
6 ----------------------------------------------------------------------
8 First we ask: What is an Instruction Set Architecture (ISA)? ISAs are
9 the lowest level at which software talks to the machine. An ISA
12 - machine code that runs on a CPU
13 - a wide-ranging description of many other aspects of the hardware
14 (Intel's ISA document is over 2000 pages long)
16 Today, ISAs are mainly owned by companies. Intel owns the x86
17 architecture used in the majority of servers and laptops. ARM owns
18 the ARM architecture used in the majority of phones and tablets. IBM
19 owns two architectures (s/390 and POWER). And there are others but
20 those are the major ones today.
22 Can you make your own x86-compatible chip?
24 No. Companies protect ISAs aggressively with patents, copyrights and
25 trade secrets. Intel and AMD cross-license patents and prevent anyone
26 else from developing x86 chips.
30 ARM operates slightly differently: their architecture is also heavily
31 defended with patents, but anyone can come along and license that
32 architecture to make their own chips, but they will pay millions up
33 front plus a few dollars for each chip they sell.
35 [SLIDE: RISC-V LOGO AND FOUNDATION MEMBERS]
37 RISC-V is different: RISC-V is an attempt to create a modern ISA which
38 is *not* covered by patents, and has a liberal open source license
39 (BSD). There are no up front costs or per unit license fees. The
40 only real limitation is use of the RISC-V Trade Mark which requires a
41 fairly modest fee, and doesn't prevent you from making chips as long
42 as you don't use the Trade Mark.
44 RISC-V is run by the RISC-V Foundation (https://riscv.org/) of which
45 IBM is a member (but not Red Hat, yet). There are hundreds of
46 companies who are members of the Foundation.
50 Let's have a look at some RISC-V machine code.
52 * Most instructions are 32 bits (4 bytes) long.
53 * Compressed instructions are 16 bits.
54 * Some instructions can be longer than 32 bits.
55 * Decoding instruction boundaries is easy, even if you can't or
56 don't fully parse them.
58 [SLIDE: RISC-V REGISTERS]
60 * 32 general purpose registers
61 * 32 floating point registers (extension)
63 * Always little-endian
64 * Influenced by MIPS architecture
65 * Proven to be patent-free
67 The architecture is "boring"! It doesn't contain any surprise
68 features. It's is meant to be as independent as possible of the
69 micro-architecture. It's simple to decode, simple to implement (at
70 least if you don't care about performance), and simple to emulate.
71 There are no weird features like register windows or branch delay
74 [SLIDE: RISC-V EXTENSIONS]
76 RISC-V is designed to be extensible. The base architectures are:
78 * RV32I = 32 bit, integer arithmetic, basic instructions like compare, jump etc
79 * RV32E = 32 bit embedded variant, 16 registers, not yet standardized
80 * RV64I = 64 bit + integers
81 * RV128I = 128 bit + integers (not yet standardized)
83 Normally you will add a few extensions. The common ones are:
85 * I = base + integer (this is not an extension, it's required)
86 * M = integer multiplication and division
87 * A = atomic operations
89 * D = double-precision floating point
90 * C = compressed instructions
93 Fedora and Debian are targetting RV64GC
95 There are other extensions too. The notable ones are:
97 * B = bit manipulation
101 [SLIDE: RISC-V SPECIFICATIONS]
103 There are two important documents:
105 * "User spec" (RISC-V ISM Vol 1) version 2.2 / 20190608
107 Covers what userspace code needs to know:
108 User instructions, Memory ordering, Calling conventions, etc.
110 * "Priv spec" (RISC-V ISM Vol 2) version 1.10 / 20190608
112 Covers what the kernel needs to know:
113 Priv instructions, Page tables,
114 Machine Status Registers, Interrupts, Timers, etc.
116 These documents are freely downloadable and distributed under a
117 Creative Commons license.
119 [SLIDE: RISC-V OPEN SOURCE IMPLEMENTATIONS]
121 At least 7 open source implementations:
123 * Rocket chip: Simple in-order processor
124 * BOOM and BOOMv2: OOO Superscalar processor
126 * Two Western Digital processors
127 * Two educational implementations that I won't talk about today
129 Rocket is the most widely used. It is written in Chisel which is a
130 Scala-based metalanguage that generates Verilog. PicoRV32 is a lot of
131 fun too: It's written in Verilog and can be programmed on to a very
132 cheap (under $40) FPGA. Great for tinkering.
134 [SLIDE: OTHER PARTS OF THE ECOSYSTEM]
136 As well as the CPU core, there are also open source implementations
139 * L1 and L2 Cache hierarchy and coherence
140 * ChipLink/TileLink: Communicate between sockets and with peripherals
141 * Interrupt controllers
144 * DDR DRAM controller
146 So you can (sort of) create your own computer.
148 There are still many missing bits:
150 * High-performance DDR
151 * High-performance ethernet
154 * Standard boot environment (although this is coming together)
156 There are three emulators:
158 * QEMU has supported RV64GC since around 2017.
159 * Spike is the RISC-V Foundation's cycle-accurate simulator
160 * Fabrice Bellard's emulator
162 There are ports of the major tools:
164 * Linux (of course!) since around 2018
165 * binutils since 2017
171 2. RISC-V and Fedora, Debian and upstream communities
172 ----------------------------------------------------------------------
174 I did the first bootstrap of Fedora in September 2016.
176 [SLIDE: BOOTSTRAPPING]
178 Bootstrapping Fedora is complicated: I started off with an x86-64 disk
179 image which could run rpmbuild. I then removed all of the x86-64
180 binaries and libraries. I replaced them with cross-compiled RISC-V
181 binaries and libraries. About 60 packages had to be cross-compiled
182 and hundreds of binaries were built.
184 After several weeks of work I ended up with a disk image which was
185 bootable under QEMU emulation, which could run rpmbuild. This was
186 called the "stage 3" disk image.
188 The stage 3 disk image allowed me to (very slowly) build RPMs
189 natively. After many more weeks of work I had built enough RPMs by
190 hand so that I could create a disk image from just RPMs. This was
191 called the "stage 4" disk image.
193 Using the stage 4 disk image we were then able to rebuild most of
194 Fedora, successively building newer and newer disk images.
196 Git repo: https://github.com/rwmjones/fedora-riscv-bootstrap
198 Initially we had a custom autobuilder which went through the whole of
199 Fedora blindly attempting to rebuild each package. We spent many
200 months fixing Fedora packages, fixing upstream programs, and manually
201 breaking dependency chains.
203 [SLIDE: SECOND AND THIRD BOOTSTRAPS]
205 Because of changes that kept breaking glibc backwards compatibility,
206 we knew that the first bootstrap wouldn't be the last one. In fact we
207 ended up doing two more bootstraps. The second was a practice one to
208 produce a "script" for bootstrapping Fedora. The third one was done
209 in February 2018 after glibc was released with a permanently stable
210 ABI. The third one should be the last one and is the basis for all
215 Nowadays we have a normal Koji builder which shadows Fedora 29, 30 and
218 [SLIDE: FEDORA RISC-V]
220 You can grab Fedora for RISC-V and run it either on the real hardware
221 or under QEMU on your laptop.
223 [I will show a demo of Fedora RISC-V, showing that it looks very much
224 like Fedora on any other architecture]
226 While we were working on Fedora, we were also working closely with the
227 Debian and upstream communities. Patches and techniques are shared
228 with upstream and with Debian.
230 To get involved with Fedora RISC-V please join us on Freenode:
238 3. Companies making RISC-V hardware
239 ----------------------------------------------------------------------
241 Initial RISC-V implementations were small-run silicon or FPGAs. It
242 wasn't until 2018 that we started to see companies producing RISC-V
243 processors and boards. It seems that most companies at the moment are
244 looking at the embedded space, and are doing this in order to save on
245 ARM licensing fees. It's still very early days.
247 Note that embedded processors (RV32) will *not* run Fedora or Debian,
248 and some won't even run Linux.
252 The RISC-V single board computer you can buy today is made by SiFive,
253 and it's called the *HiFive Unleashed*. I have two of these, and we
254 have 4 or 5 in total across Red Hat.
256 This uses the Rocket chip design, with 4 cores. It's mostly open
257 source. SiFive also have a 32 bit embedded single board computer.
275 4. RISC-V on the Server
276 ----------------------------------------------------------------------
278 [This section will be a more free-form discussion about servers and
279 whether RISC-V will ever capture any significant share of the
280 marketplace. Here I just outline topics for discussion.]
282 * What is a server? What is the difference between a server and a
283 laptop? What specialized components go into a server?
285 - NUMA and interrupt routing
286 - headless remote management and BMC
287 - very high speed network interfaces, RDMA
288 - separation of storage from compute, SANs, iSCSI, FC
289 - GPGPU, TPU, custom hardware
290 - hardware offload and accelerators
291 - virtualization, NFV, SR-IOV, ...
294 * How is server hardware deployed? Single servers versus datacenters.
296 * How is server software provisioned?
298 - mass provisioning of nodes (eg. with Ironic)
299 - orchestration and configuration management
301 * Single kernel image works everywhere.
303 * Standard boot method.
305 * Hardware discovery.
309 - distributed computing, fast fail-over, containers, etc.
310 - mainframe-style redundancy