3 - What precisely is offered by RISC-V?
5 - Bootstrapping Fedora.
7 - The state of RISC-V software development and the community.
9 - Are open source ISAs in Red Hat's future?
11 ----------------------------------------------------------------------
15 fixed size 32 bit instructions
16 compressed instructions extension
17 32 general purpose registers
18 32 floating point registers (extension)
22 proven to be patent-free
26 Micro-architecture independent as far as possible
28 No register windows, branch delay slots etc
29 Royalty free, no licensing
34 Priv spec 1.7 -> 1.9/2.0
36 4 open source core designs, Rocket, BOOM and two others
37 Chisel generates Verilog
38 Includes cache hierarchy
39 Includes coherence between L2 caches
41 Targets C++ (simulation), FPGA or ASIC
42 Proprietary tools needed if you go FPGA or ASIC route
49 LowRISC = "RPi for grown-ups"
51 Many FPGA implementations
52 Lots of research groups
53 Lots of small dev groups
55 Some large companies looking: NVidia, Google, AMD, HPE, IBM, Mellanox,
56 Microsemi, Microsoft, WD, ...
60 any other sort of hardware, serial, ethernet, display, SATA, DDR, ...
61 PCI (SiFive have done some work)
62 much of this is filled in with proprietary "IP"
65 ----------------------------------------------------------------------
72 Explain why: current software is crap
74 Almost like an embedded system
78 Four stage bootstrap process
79 Stage 3 is a "hack job" containing a mix of cross-compiled
80 packages built on the host, layered with "--nodeps"-installed RPMs on top.
82 Stage 4 is the clean image built entirely from RPMs, with all
83 dependencies satisfied and all files controlled by RPM.
85 ----------------------------------------------------------------------
87 Software development and the community
89 ----------------------------------------------------------------------