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5 <h1>What is RISC-V?</h1>
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8 val id_illegal_insn = !id_ctrl.legal ||
9 id_ctrl.div && !csr.io.status.isa('m'-'a') ||
10 id_ctrl.amo && !csr.io.status.isa('a'-'a') ||
11 id_ctrl.fp && !(csr.io.status.fs.orR && csr.io.status.isa('f'-'a')) ||
12 id_ctrl.dp && !csr.io.status.isa('d'-'a') ||
13 ibuf.io.inst(0).bits.rvc && !csr.io.status.isa('c'-'a') ||
14 id_ctrl.rocc && !(csr.io.status.xs.orR && csr.io.status.isa('x'-'a'))
15 // stall decode for fences (now, for AMO.aq; later, for AMO.rl and FENCE)
16 val id_amo_aq = id_inst(0)(26)
17 val id_amo_rl = id_inst(0)(25)
18 val id_fence_next = id_ctrl.fence || id_ctrl.amo && id_amo_rl
19 val id_mem_busy = !io.dmem.ordered || io.dmem.req.valid
20 val id_rocc_busy = Bool(usingRoCC) &&
21 (io.rocc.busy || ex_reg_valid && ex_ctrl.rocc ||
22 mem_reg_valid && mem_ctrl.rocc || wb_reg_valid && wb_ctrl.rocc)
23 id_reg_fence := id_fence_next || id_reg_fence && id_mem_busy
24 val id_do_fence = id_rocc_busy && id_ctrl.fence ||
25 id_mem_busy && (id_ctrl.amo && id_amo_aq || id_ctrl.fence_i || id_reg_fence
26 && (id_ctrl.mem || id_ctrl.rocc) || id_csr_en)