From: Richard W.M. Jones Date: Thu, 15 Sep 2016 13:24:46 +0000 (+0100) Subject: Initial work. X-Git-Url: http://git.annexia.org/?a=commitdiff_plain;ds=sidebyside;h=6b04b2b08a76ab29b1d63794159f6deea2cf9a7c;p=riscv-talks.git Initial work. --- diff --git a/2016-redhat/.gitignore b/2016-redhat/.gitignore new file mode 100644 index 0000000..317d723 --- /dev/null +++ b/2016-redhat/.gitignore @@ -0,0 +1,4 @@ +*~ + +/bindings +/history diff --git a/2016-redhat/0000-introduction.html b/2016-redhat/0000-introduction.html new file mode 100644 index 0000000..ed38404 --- /dev/null +++ b/2016-redhat/0000-introduction.html @@ -0,0 +1,27 @@ + + + + +
+

+ RISC-V —
+ free and open Instruction Set Architecture +

+

+ Monday 26th September 2016
+ Richard W.M. Jones
+ < rjones @ redhat.com > +

+

+ RISC-V ("Risc Five") + is a new + Instruction Set Architecture (ISA) with a BSD license which + aims to become the standard open architecture for industry. +

+

+ This talk covers: What precisely is offered by RISC-V? + Bootstrapping + Fedora on RISC-V. The state of RISC-V software development + and the community. Are open source ISAs in Red Hat's future? +

+
diff --git a/2016-redhat/1000-cores.html b/2016-redhat/1000-cores.html new file mode 100644 index 0000000..a7c7f6d --- /dev/null +++ b/2016-redhat/1000-cores.html @@ -0,0 +1,7 @@ + + + + +

It's real!

+ + diff --git a/2016-redhat/2000-what-is-riscv.html b/2016-redhat/2000-what-is-riscv.html new file mode 100644 index 0000000..5ed1464 --- /dev/null +++ b/2016-redhat/2000-what-is-riscv.html @@ -0,0 +1,19 @@ + + + + +

What is RISC-V?

+ + diff --git a/2016-redhat/2010-instructions.html b/2016-redhat/2010-instructions.html new file mode 100644 index 0000000..248e382 --- /dev/null +++ b/2016-redhat/2010-instructions.html @@ -0,0 +1,32 @@ + + + + +

What is RISC-V?

+ +
+00370613   addi    a2,a4,3
+02c13c23   sd      a2,56(sp)
+02d108a3   sb      a3,49(sp)
+00274703   lbu     a4,2(a4)
+03d00793   li      a5,61
+3cf70863   beq     a4,a5,1ce28 <main+0x1d68>
+000165b7   lui     a1,0x16
+c3058593   addi    a1,a1,-976 # 15c30 <__mon_yday+0x24d8>
+00500613   li      a2,5
+00000513   li      a0,0
+964fe0ef   jal     1abd0 <dcgettext@plt>
+00050613   mv      a2,a0
+00000593   li      a1,0
+00000513   li      a0,0
+f75fd0ef   jal     1a9f0 <error@plt>
+9901b503   ld      a0,-1648(gp) # 16bd8 <color_buf>
+accfe0ef   jal     1ad50 <free@plt>
+9981b503   ld      a0,-1640(gp) # 16be0 <color_ext_list>
+00050a63   beqz    a0,1caa0 <main+0x19e0>
+02053983   ld      s3,32(a0)
+abcfe0ef   jal     1ad50 <free@plt>
+00098513   mv      a0,s3
+ff1ff06f   j       1ca8c <main+0x19cc>
+9a0180a3   sb      zero,-1631(gp) # 16be9 <print_with_color>
+
diff --git a/2016-redhat/2020-boring.html b/2016-redhat/2020-boring.html new file mode 100644 index 0000000..6da920b --- /dev/null +++ b/2016-redhat/2020-boring.html @@ -0,0 +1,15 @@ + + + + +

What is RISC-V?

+ +
+“[RISC-V]'s not supposed to be "different from other architectures". +It's supposed to be as familiar as possible to compiler writers and +CPU designers, minimizing novelty and surprises and maximizing +precedent so that it can become the Standard Boring ISA.”
+
+

+— Stefan O'Rear on the isa-dev mailing list +

diff --git a/2016-redhat/2030-specifications.html b/2016-redhat/2030-specifications.html new file mode 100644 index 0000000..fe7bbdd --- /dev/null +++ b/2016-redhat/2030-specifications.html @@ -0,0 +1,7 @@ + + + + +

What is RISC-V?

+ + diff --git a/2016-redhat/2040-open-source-cores.html b/2016-redhat/2040-open-source-cores.html new file mode 100644 index 0000000..74484a7 --- /dev/null +++ b/2016-redhat/2040-open-source-cores.html @@ -0,0 +1,12 @@ + + + + +

What is RISC-V?

+ + diff --git a/2016-redhat/2050-chisel.html b/2016-redhat/2050-chisel.html new file mode 100644 index 0000000..938e9a9 --- /dev/null +++ b/2016-redhat/2050-chisel.html @@ -0,0 +1,27 @@ + + + + +

What is RISC-V?

+ +
+val id_illegal_insn = !id_ctrl.legal ||
+    id_ctrl.div && !csr.io.status.isa('m'-'a') ||
+    id_ctrl.amo && !csr.io.status.isa('a'-'a') ||
+    id_ctrl.fp && !(csr.io.status.fs.orR && csr.io.status.isa('f'-'a')) ||
+    id_ctrl.dp && !csr.io.status.isa('d'-'a') ||
+    ibuf.io.inst(0).bits.rvc && !csr.io.status.isa('c'-'a') ||
+    id_ctrl.rocc && !(csr.io.status.xs.orR && csr.io.status.isa('x'-'a'))
+// stall decode for fences (now, for AMO.aq; later, for AMO.rl and FENCE)
+val id_amo_aq = id_inst(0)(26)
+val id_amo_rl = id_inst(0)(25)
+val id_fence_next = id_ctrl.fence || id_ctrl.amo && id_amo_rl
+val id_mem_busy = !io.dmem.ordered || io.dmem.req.valid
+val id_rocc_busy = Bool(usingRoCC) &&
+    (io.rocc.busy || ex_reg_valid && ex_ctrl.rocc ||
+     mem_reg_valid && mem_ctrl.rocc || wb_reg_valid && wb_ctrl.rocc)
+id_reg_fence := id_fence_next || id_reg_fence && id_mem_busy
+val id_do_fence = id_rocc_busy && id_ctrl.fence ||
+    id_mem_busy && (id_ctrl.amo && id_amo_aq || id_ctrl.fence_i || id_reg_fence
+                            && (id_ctrl.mem || id_ctrl.rocc) || id_csr_en)
+
diff --git a/2016-redhat/2060-emulators.html b/2016-redhat/2060-emulators.html new file mode 100644 index 0000000..5e002f1 --- /dev/null +++ b/2016-redhat/2060-emulators.html @@ -0,0 +1,10 @@ + + + + +

What is RISC-V?

+ + diff --git a/2016-redhat/2070-toolchain.html b/2016-redhat/2070-toolchain.html new file mode 100644 index 0000000..f26ac21 --- /dev/null +++ b/2016-redhat/2070-toolchain.html @@ -0,0 +1,12 @@ + + + + +

What is RISC-V?

+ + diff --git a/2016-redhat/2080-external-groups.html b/2016-redhat/2080-external-groups.html new file mode 100644 index 0000000..0e0843f --- /dev/null +++ b/2016-redhat/2080-external-groups.html @@ -0,0 +1,13 @@ + + + + +

What is RISC-V?

+ + diff --git a/2016-redhat/2090-external-companies.html b/2016-redhat/2090-external-companies.html new file mode 100644 index 0000000..666473d --- /dev/null +++ b/2016-redhat/2090-external-companies.html @@ -0,0 +1,18 @@ + + + + +

What is RISC-V?

+ + diff --git a/2016-redhat/2500-whats-missing.html b/2016-redhat/2500-whats-missing.html new file mode 100644 index 0000000..0ed1e72 --- /dev/null +++ b/2016-redhat/2500-whats-missing.html @@ -0,0 +1,20 @@ + + + + +

What missing from RISC-V?

+ + + +

+Not enough to make a real processor or SoC +

diff --git a/2016-redhat/bashrc b/2016-redhat/bashrc new file mode 100644 index 0000000..4c6a3c6 --- /dev/null +++ b/2016-redhat/bashrc @@ -0,0 +1,17 @@ +# -*- shell-script -*- + +# Colour ls. +if [ -f /etc/profile.d/colorls.sh ]; then . /etc/profile.d/colorls.sh; fi + +# Fancy prompt colours (see +# https://wiki.archlinux.org/index.php/Color_Bash_Prompt) +promptcol='\e[0;32m' ;# colour for the prompt +commandcol='\e[1;31m' ;# colour for the typed command +outputcol='\e[0m' ;# colour for command output + +export PS1="\n\[$promptcol\]\$ \[$commandcol\]" + +trap 'echo -ne "$outputcol"' DEBUG + +# Load key bindings (if any). +bind -f $talkdir/bindings diff --git a/2016-redhat/code.js b/2016-redhat/code.js new file mode 100644 index 0000000..e69de29 diff --git a/2016-redhat/cores.png b/2016-redhat/cores.png new file mode 100644 index 0000000..19ccfc4 Binary files /dev/null and b/2016-redhat/cores.png differ diff --git a/2016-redhat/cores.xcf b/2016-redhat/cores.xcf new file mode 100644 index 0000000..f812c1b Binary files /dev/null and b/2016-redhat/cores.xcf differ diff --git a/2016-redhat/notes.txt b/2016-redhat/notes.txt new file mode 100644 index 0000000..5ea3c55 --- /dev/null +++ b/2016-redhat/notes.txt @@ -0,0 +1,74 @@ +Talk contents: + + - What precisely is offered by RISC-V? + + - Bootstrapping Fedora. + + - The state of RISC-V software development and the community. + + - Are open source ISAs in Red Hat's future? + +---------------------------------------------------------------------- + +Instructions: + +fixed size 32 bit instructions +compressed instructions extension +32 general purpose registers +32 floating point registers (extension) +zero register +influenced by MIPS +proven to be patent-free + +Boring: + +Micro-architecture independent as far as possible +Micro-op fusion +No register windows, branch delay slots etc +Royalty free, no licensing + +Specifications: + + User spec 2.0 -> 2.1 + Priv spec 1.7 -> 1.9/2.0 + +4 open source core designs, Rocket, BOOM and two others + Chisel generates Verilog + Includes cache hierarchy + Includes coherence between L2 caches + Parameterized + Targets C++ (simulation), FPGA or ASIC + Proprietary tools needed if you go FPGA or ASIC route + +Emulators + +Toolchain + +External projects: + LowRISC = "RPi for grown-ups" + SiFive + Many FPGA implementations + Lots of research groups + Lots of small dev groups + +Some large companies looking: NVidia, Google, AMD, HPE, IBM, Mellanox, +Microsemi, Microsoft, WD, ... + +Missing bits: + PLIC (coming) + any other sort of hardware, serial, ethernet, display, SATA, DDR, ... + PCI (SiFive have done some work) + much of this is filled in with proprietary "IP" + "Minion cores" + +---------------------------------------------------------------------- + +Fedora + +---------------------------------------------------------------------- + +Software development and the community + +---------------------------------------------------------------------- + +Red Hat diff --git a/2016-redhat/redhat.png b/2016-redhat/redhat.png new file mode 100644 index 0000000..f50076a Binary files /dev/null and b/2016-redhat/redhat.png differ diff --git a/2016-redhat/specs.png b/2016-redhat/specs.png new file mode 100644 index 0000000..37411cc Binary files /dev/null and b/2016-redhat/specs.png differ diff --git a/2016-redhat/specs.xcf b/2016-redhat/specs.xcf new file mode 100644 index 0000000..fbf6ad6 Binary files /dev/null and b/2016-redhat/specs.xcf differ diff --git a/2016-redhat/style.css b/2016-redhat/style.css new file mode 100644 index 0000000..4a33b8f --- /dev/null +++ b/2016-redhat/style.css @@ -0,0 +1,67 @@ +/* Red Hat red is rgb(204,0,0). */ + +body { + background: url(redhat.png) no-repeat; + background-position: 98% 0; + /* font-size: 28pt; */ /* For max */ + font-size: 20pt; /* For 1024x768 */ + /* font-family: liberation, helvetica; */ + font-family: helvetica; +} + +body td, body th { /* why?? */ + font-size: 24pt; + padding-bottom: 8px; +} + +h1 { + color: rgb(204,0,0); + /*font-size: 48px;*/ + font-size: 40px; + top: 8; + left: 0; + border-bottom: 2px solid rgb(204,0,0); +} + +b { + color: rgb(204,0,0); +} + +div#titlepage { + margin-top: 100px; + text-align: center; +} + +div#titlepage p.title { + color: rgb(204,0,0); + font-weight: bold; + font-size: 48px; +} + +div#titlepage author { + font-size: 36px; +} + +/* Code */ +pre.code { + margin-left: 1em; + background: #eee; +} + +code { + color: rgb(204,0,0); +} + +/* Bullet points */ +li { + padding-bottom: 16px; +} + +/* Logo */ +img#fish { + position: absolute; + top: 128px; + right: 32px; + width: 200px; + /*height: 256px;*/ +} \ No newline at end of file