X-Git-Url: http://git.annexia.org/?a=blobdiff_plain;f=Makefile;h=edf97862b855e5af19ed73409621240c51717ec8;hb=67d2ef5b900e97d527838d5a622fd15754db8460;hp=041dfbca8423dfd717470b66e6985174eefa6092;hpb=8a745cd28cf55dbc253648c0c8ba0a1f00f588b9;p=fedora-riscv.git

diff --git a/Makefile b/Makefile
index 041dfbc..edf9786 100644
--- a/Makefile
+++ b/Makefile
@@ -7,6 +7,10 @@
 # https://github.com/riscv/riscv-pk/issues/18#issuecomment-206115996
 RISCV_QEMU_COMMIT               = 94f5eb73091fb4fe272db3e943f173ecc0f78ffd
 RISCV_QEMU_SHORTCOMMIT          = 94f5eb73
+RISCV_FESVR_COMMIT              = 0f34d7ad311f78455a674224225f5b3056efba1d
+RISCV_FESVR_SHORTCOMMIT         = 0f34d7ad
+RISCV_ISA_SIM_COMMIT            = 3bfc00ef2a1b1f0b0472a39a866261b00f67027e
+RISCV_ISA_SIM_SHORTCOMMIT       = 3bfc00ef
 RISCV_GNU_TOOLCHAIN_COMMIT      = 728afcddcb0526a0f6560c4032da82805f054d58
 RISCV_GNU_TOOLCHAIN_SHORTCOMMIT = 728afcdd
 RISCV_PK_COMMIT                 = 85ae17aa149b9ea114bdd70cc30ea7e73813fb48
@@ -25,7 +29,13 @@ all: stage1 stage2 stage3 stage4
 
 stage1: stage1-riscv-qemu/riscv-qemu-$(RISCV_QEMU_SHORTCOMMIT).tar.gz \
 	stage1-riscv-qemu/riscv-qemu.spec \
-	stamp-riscv-qemu-installed
+	stamp-riscv-qemu-installed \
+	stage1-riscv-fesvr/riscv-fesvr-$(RISCV_FESVR_SHORTCOMMIT).tar.gz \
+	stage1-riscv-fesvr/riscv-fesvr.spec \
+	stamp-riscv-fesvr-installed \
+	stage1-riscv-isa-sim/riscv-isa-sim-$(RISCV_ISA_SIM_SHORTCOMMIT).tar.gz \
+	stage1-riscv-isa-sim/riscv-isa-sim.spec \
+	stamp-riscv-isa-sim-installed
 
 stage1-riscv-qemu/riscv-qemu-$(RISCV_QEMU_SHORTCOMMIT).tar.gz:
 	rm -f $@ $@-t
@@ -57,6 +67,56 @@ stamp-riscv-qemu-installed:
 	}
 	touch $@
 
+stage1-riscv-fesvr/riscv-fesvr-$(RISCV_FESVR_SHORTCOMMIT).tar.gz:
+	rm -f $@ $@-t
+	wget -O $@-t 'https://github.com/riscv/riscv-fesvr/archive/$(RISCV_FESVR_COMMIT)/riscv-fesvr-$(RISCV_FESVR_SHORTCOMMIT).tar.gz'
+	mv $@-t $@
+
+stage1-riscv-fesvr/riscv-fesvr.spec: stage1-riscv-fesvr/riscv-fesvr.spec.in
+	sed -e 's/@COMMIT@/$(RISCV_FESVR_COMMIT)/g' \
+	    -e 's/@SHORTCOMMIT@/$(RISCV_FESVR_SHORTCOMMIT)/g' \
+	    < $^ > $@-t
+	mv $@-t $@
+
+stamp-riscv-fesvr-installed:
+	rm -f $@
+	@rpm -q riscv-fesvr >/dev/null || { \
+	  echo "ERROR: You must install riscv-fesvr:"; \
+	  echo; \
+	  echo "       dnf copr enable rjones/riscv"; \
+	  echo "       dnf install riscv-fesvr"; \
+	  echo; \
+	  echo "OR: you can build it yourself from the stage1-riscv-fesvr directory."; \
+	  echo; \
+	  exit 1; \
+	}
+	touch $@
+
+stage1-riscv-isa-sim/riscv-isa-sim-$(RISCV_ISA_SIM_SHORTCOMMIT).tar.gz:
+	rm -f $@ $@-t
+	wget -O $@-t 'https://github.com/riscv/riscv-isa-sim/archive/$(RISCV_ISA_SIM_COMMIT)/riscv-isa-sim-$(RISCV_ISA_SIM_SHORTCOMMIT).tar.gz'
+	mv $@-t $@
+
+stage1-riscv-isa-sim/riscv-isa-sim.spec: stage1-riscv-isa-sim/riscv-isa-sim.spec.in
+	sed -e 's/@COMMIT@/$(RISCV_ISA_SIM_COMMIT)/g' \
+	    -e 's/@SHORTCOMMIT@/$(RISCV_ISA_SIM_SHORTCOMMIT)/g' \
+	    < $^ > $@-t
+	mv $@-t $@
+
+stamp-riscv-isa-sim-installed:
+	rm -f $@
+	@rpm -q riscv-isa-sim >/dev/null || { \
+	  echo "ERROR: You must install riscv-isa-sim:"; \
+	  echo; \
+	  echo "       dnf copr enable rjones/riscv"; \
+	  echo "       dnf install riscv-isa-sim"; \
+	  echo; \
+	  echo "OR: you can build it yourself from the stage1-riscv-isa-sim directory."; \
+	  echo; \
+	  exit 1; \
+	}
+	touch $@
+
 # Stage 2
 
 stage2: stage2-riscv-gnu-toolchain/riscv-gnu-toolchain-$(RISCV_GNU_TOOLCHAIN_SHORTCOMMIT).tar.gz \
@@ -80,9 +140,15 @@ stage2-riscv-gnu-toolchain/binutils-$(BINUTILS_VERSION).tar.gz:
 	wget -O $@-t http://mirrors.kernel.org/gnu/binutils/binutils-$(BINUTILS_VERSION).tar.gz
 	mv $@-t $@
 
+# GCC 5 no longer compiles with GCC 6 unless we patch it.
+# https://gcc.gnu.org/bugzilla/show_bug.cgi?id=69959
 stage2-riscv-gnu-toolchain/gcc-$(GCC_VERSION).tar.gz:
 	rm -f $@ $@-t
 	wget -O $@-t http://mirrors.kernel.org/gnu/gcc/gcc-$(GCC_VERSION)/gcc-$(GCC_VERSION).tar.gz
+	zcat $@-t | tar xf -
+	cd gcc-$(GCC_VERSION) && patch -p0 < ../stage2-riscv-gnu-toolchain/gcc-5-fix-compilation-with-gcc-6.patch
+	tar zcf $@-t gcc-$(GCC_VERSION)
+	rm -r gcc-$(GCC_VERSION)
 	mv $@-t $@
 
 stage2-riscv-gnu-toolchain/glibc-$(GLIBC_VERSION).tar.gz: