X-Git-Url: http://git.annexia.org/?a=blobdiff_plain;f=2019-redhat%2F2019-riscv-talk.txt;h=5089f00b9fdfc58ab3f53b3ba206b159ee09dd86;hb=cd5c02e76c817cf91b0249ac1f88031e59b75df1;hp=3fae7cf53c14928666b30539c7438727da069fb5;hpb=ccd60c8af7ff3d6742c11fbce274fbec71750a3b;p=riscv-talks.git diff --git a/2019-redhat/2019-riscv-talk.txt b/2019-redhat/2019-riscv-talk.txt index 3fae7cf..5089f00 100644 --- a/2019-redhat/2019-riscv-talk.txt +++ b/2019-redhat/2019-riscv-talk.txt @@ -118,17 +118,18 @@ Creative Commons license. [SLIDE: RISC-V OPEN SOURCE IMPLEMENTATIONS] -At least 5 open source implementations: +At least 7 open source implementations: * Rocket chip: Simple in-order processor * BOOM and BOOMv2: OOO Superscalar processor * PicoRV32 + * Two Western Digital processors * Two educational implementations that I won't talk about today Rocket is the most widely used. It is written in Chisel which is a Scala-based metalanguage that generates Verilog. PicoRV32 is a lot of fun too: It's written in Verilog and can be programmed on to a very -cheap (under $40) FPGA. +cheap (under $40) FPGA. Great for tinkering. [SLIDE: OTHER PARTS OF THE ECOSYSTEM] @@ -152,10 +153,11 @@ There are still many missing bits: * BMC management * Standard boot environment (although this is coming together) -There are two emulators: +There are three emulators: * QEMU has supported RV64GC since around 2017. * Spike is the RISC-V Foundation's cycle-accurate simulator + * Fabrice Bellard's emulator There are ports of the major tools: @@ -171,6 +173,8 @@ There are ports of the major tools: I did the first bootstrap of Fedora in September 2016. +[SLIDE: BOOTSTRAPPING] + Bootstrapping Fedora is complicated: I started off with an x86-64 disk image which could run rpmbuild. I then removed all of the x86-64 binaries and libraries. I replaced them with cross-compiled RISC-V @@ -208,8 +212,8 @@ current work. [SLIDE: KOJI] -Nowadays with have a normal Koji builder which shadows Fedora 29, 30 -and Rawhide. +Nowadays we have a normal Koji builder which shadows Fedora 29, 30 and +Rawhide. [SLIDE: FEDORA RISC-V] @@ -219,27 +223,88 @@ or under QEMU on your laptop. [I will show a demo of Fedora RISC-V, showing that it looks very much like Fedora on any other architecture] -[SLIDE: DEBIAN] - While we were working on Fedora, we were also working closely with the -Debian and upstream communities. Changes and tips are shared with -upstream and with Debian. +Debian and upstream communities. Patches and techniques are shared +with upstream and with Debian. + +To get involved with Fedora RISC-V please join us on Freenode: + + #fedora-riscv + +[SLIDE: DEBIAN] 3. Companies making RISC-V hardware ---------------------------------------------------------------------- +Initial RISC-V implementations were small-run silicon or FPGAs. It +wasn't until 2018 that we started to see companies producing RISC-V +processors and boards. It seems that most companies at the moment are +looking at the embedded space, and are doing this in order to save on +ARM licensing fees. It's still very early days. + +Note that embedded processors (RV32) will *not* run Fedora or Debian, +and some won't even run Linux. +[SLIDE: SIFIVE] +The RISC-V single board computer you can buy today is made by SiFive, +and it's called the *HiFive Unleashed*. I have two of these, and we +have 4 or 5 in total across Red Hat. +This uses the Rocket chip design, with 4 cores. It's mostly open +source. SiFive also have a 32 bit embedded single board computer. +[SLIDE: OTHERS] + + * SHAKTI + * Andes N25 and NX25 + * Kendryte + * Codasip + * Syntacore + * Nvidia + * Western Digital + * lowRISC + * PULPino + * Esperanto + * Adapteva 4. RISC-V on the Server ---------------------------------------------------------------------- +[This section will be a more free-form discussion about servers and +whether RISC-V will ever capture any significant share of the +marketplace. Here I just outline topics for discussion.] + +* What is a server? What is the difference between a server and a + laptop? What specialized components go into a server? + + - NUMA and interrupt routing + - headless remote management and BMC + - very high speed network interfaces, RDMA + - separation of storage from compute, SANs, iSCSI, FC + - GPGPU, TPU, custom hardware + - hardware offload and accelerators + - virtualization, NFV, SR-IOV, ... + - fencing + +* How is server hardware deployed? Single servers versus datacenters. + +* How is server software provisioned? + + - mass provisioning of nodes (eg. with Ironic) + - orchestration and configuration management + +* Single kernel image works everywhere. + +* Standard boot method. +* Hardware discovery. +* Reliability + - distributed computing, fast fail-over, containers, etc. + - mainframe-style redundancy