X-Git-Url: http://git.annexia.org/?a=blobdiff_plain;f=2016-redhat%2F2020-boring.html;h=029db44cc48ea3f880ab9654217e14a93eed4f4b;hb=6c7d7d8130d30825327c94058e3cbe86d1d509f6;hp=6da920b6e88e6b038b81e64ab1f736be82f89227;hpb=6b04b2b08a76ab29b1d63794159f6deea2cf9a7c;p=riscv-talks.git

diff --git a/2016-redhat/2020-boring.html b/2016-redhat/2020-boring.html
index 6da920b..029db44 100644
--- a/2016-redhat/2020-boring.html
+++ b/2016-redhat/2020-boring.html
@@ -4,11 +4,11 @@
 
 <h1>What is RISC-V?</h1>
 
-<blockquote>
-<i>“[RISC-V]'s not supposed to be "different from other architectures".
+<blockquote style="margin-top: 20%;">
+<i><q>[RISC-V]'s not supposed to be "different from other architectures".
 It's supposed to be as familiar as possible to compiler writers and
 CPU designers, minimizing novelty and surprises and maximizing
-precedent so that it can become the <b>Standard Boring ISA</b>.”</i> <br/>
+precedent so that it can become the <b>Standard Boring ISA</b>.</q></i> <br/>
 </blockquote>
 <p style="text-align: right; margin-right: 3em;">
 &mdash; Stefan O'Rear on <a href="https://groups.google.com/a/groups.riscv.org/forum/#!forum/isa-dev">the isa-dev mailing list</a>