Talk contents: - What precisely is offered by RISC-V? - Bootstrapping Fedora. - The state of RISC-V software development and the community. - Are open source ISAs in Red Hat's future? ---------------------------------------------------------------------- Instructions: fixed size 32 bit instructions compressed instructions extension 32 general purpose registers 32 floating point registers (extension) zero register always little-endian influenced by MIPS proven to be patent-free Boring: Micro-architecture independent as far as possible Micro-op fusion No register windows, branch delay slots etc Royalty free, no licensing Specifications: User spec 2.0 -> 2.1 Priv spec 1.7 -> 1.9/2.0 4 open source core designs, Rocket, BOOM and two others Chisel generates Verilog Includes cache hierarchy Includes coherence between L2 caches Parameterized Targets C++ (simulation), FPGA or ASIC Proprietary tools needed if you go FPGA or ASIC route Emulators Toolchain External projects: LowRISC = "RPi for grown-ups" SiFive Many FPGA implementations Lots of research groups Lots of small dev groups Some large companies looking: NVidia, Google, AMD, HPE, IBM, Mellanox, Microsemi, Microsoft, WD, ... Missing bits: PLIC (coming) any other sort of hardware, serial, ethernet, display, SATA, DDR, ... PCI (SiFive have done some work) much of this is filled in with proprietary "IP" "Minion cores" ---------------------------------------------------------------------- Fedora Demo Aims Explain why: current software is crap Busybox Almost like an embedded system Scope Four stage bootstrap process Stage 3 is a "hack job" containing a mix of cross-compiled packages built on the host, layered with "--nodeps"-installed RPMs on top. Stage 4 is the clean image built entirely from RPMs, with all dependencies satisfied and all files controlled by RPM. ---------------------------------------------------------------------- Software development and the community ---------------------------------------------------------------------- Red Hat